Modern electronic devices, especially semiconductor (SC) devices and integrated circuits (ICs) are at risk of damage due to electrostatic discharge (ESD) events. It is well known that electrostatic discharge from handling SC devices and ICs, by humans or machines or both, is a source of such excess voltage. Accordingly, it is commonplace to provide an ESD clamp (voltage limiting device) across the input/output (I/O) and other terminals of such SC devices and IC's.
FIG. 1 is a simplified schematic diagram of circuit 20 according to the prior art, wherein ESD clamp 23 is placed between input/output (I/O) terminal or pad 21 and ground or common terminal 24 of a SC device or IC to protect device(s) or IC 22 (the “protected core”) that is also coupled typically to I/O terminal or pad 21 and common (e.g., “GND”) terminal 24. As used herein, the abbreviation “GND” is intended to refer to the common or reference terminal of a particular circuit or electronic element, irrespective of whether it is actually coupled to an earth return, and the abbreviation “I/O” is intended to include any external terminal other than “GND” and the legend “protected core” is intended to include any individual device or collection of devices or electronic elements, such as are found for example (and not intended to be limiting) in integrated circuits (ICs) and RF amplifiers.
Zener diode symbol 23′ within ESD clamp 23 indicates that the function of ESD clamp 23 is to limit the voltage than can appear across protected core 22 irrespective of the voltage applied between I/O pad 21 and GND or reference terminal 24. It should be understood that ESD clamp 23 is not limited to Zener diodes but can include any combination of devices that switches ON at a predetermined voltage V sufficiently low to protect circuit core 22 from an ESD or other excess voltage event and that remains substantially OFF at voltages below V so as to not interfere with normal operation of protected core 22 of circuit 20. As indicated by Zener diode symbol 23′, ESD clamp 23 is an asymmetric or unidirectional clamp, that is, the voltages at which it conducts (turns-ON) are significantly different for the two polarities of applied voltage, hence the designation “asymmetric”. In its simplest form, ESD clamp 23 can go into forward conduction at a low voltage V=Vf (e.g., where |Vf|˜1 volt or less) of a first polarity and for the opposite (reverse) polarity remain OFF until a significantly larger breakdown voltage V=VBD is reached, when it then turns ON to sink an ESD event of that polarity. Below |V|˜|VBD|, such device is essentially a unidirectional device, being conductive for one polarity and non-conductive for the opposite polarity.
FIG. 2 shows current-voltage plot 28, wherein trace 20′ illustrates current 25 (see FIG. 1) flowing through ESD clamp 23 as function of the voltage applied between pad 21 and GND or reference terminal 24. The identification of positive (+) and negative (−) voltage refers to the polarity of voltage applied to I/O pad 21 with respect to terminal 24. In region 27 of plot 28 where positive (+) voltage is applied to I/O pad 21, ESD clamp 23 is reverse biased and does not conduct significantly until voltage V=+V1 is reached, whereupon it turns ON so as to shunt current 25 caused by any excess ESD voltage to terminal 24. In region 29 of plot 28, ESD clamp 23 is forward biased and goes into forward conduction at voltage V=−V2 determined generally by the band-gap of the SC material of which it is formed. As illustrated in FIG. 2, the magnitude of forward voltage drop V2 is usually small compared to the magnitude of reverse breakdown voltage V1 and is typically of the order of about a volt or less.
A problem with the circuit of FIG. 1 is that if the signal(s) being applied to I/O pad 21 go negative with respect to reference terminal 24, they can be clipped by ESD clamp 23. This is undesirable, especially in connection with analog circuitry where both positive and negative going signals are routinely encountered. The problem can be especially troublesome in connection with RF power amplifiers, which are much used in modern day communication systems. While symmetrical ESD clamps are known, that is, ESD clamps that turn on at voltages of the order of, say, V1 in either polarity, such symmetrical ESD clamps are sometimes difficult or impossible to fabricate in connection with certain types of protected devices or circuits (e.g., protected core 22) because the available fabrication steps or technology do not lend themselves to providing the specific device regions needed to form conventional symmetrical ESD clamps and modification of the manufacturing process to accommodate formation of symmetrical ESD devices may be undesirably expensive. Thus, a need continues to exist for ESD clamps that avoid the signal clipping problems associated with prior art ESD clamps of the type illustrated in FIG. 1 and that are compatible with the fabrication technology available for forming the protected devices or ICs (e.g., protected core 22), even though they may not be well suited to formation of conventional symmetrical ESD clamps. A further important consideration is providing suitable ESD clamps, clamp circuits and systems that occupy minimum SC area so as to not increase the manufacturing cost of the overall device or IC of which the ESD system is a part. It is well known that the cost of SC components and ICs increases as the chip area they occupy increases.